Physical Design Engineer � PnR / PPA / Timing Closure

Position: Physical Design Engineer - PnR / PPA / Timing Closure

Location: Austin, TX

Experience: 5+ years

Age of Profile: Please note that 18+ years of experience is not being considered Compensation

• 5-10 years: Up to $140K annually, including 10% QPLC
• 10+ years: Up to $163K annually, including 10% QPLC

Position Details Google: Open to both FTE and Contract options

Client: FTE only

Key Responsibilities

• Drive block-level physical design implementation from netlist to GDSII
• Perform floorplanning, power planning, placement, CTS, routing, and physical verification
• Optimize designs for Power, Performance, and Area (PPA)
• Drive timing closure across multiple modes and corners
• Resolve setup, hold, transition, capacitance, and noise violations
• Develop and maintain SDC timing constraints and STA signoff methodologies
• Perform EMIR (Electromigration & IR Drop) analysis and closure
• Collaborate with RTL, DFT, STA, and Signoff teams through tapeout
• Debug physical design issues and drive design convergence

Required Technical Skills

• Strong Physical Design / PnR experience
• Floorplanning, Placement & Optimization, CTS, Routing
• Timing Closure / STA / SDC
• EMIR Analysis
• PPA Optimization
• Synopsys Fusion Compiler / ICC2
• PrimeTime
• Cadence Innovus is a plus
• RedHawk / Voltus for EMIR
• Experience with advanced technology nodes such as 7nm / 5nm / 3nm is preferred
• Good understanding of low-power design and signoff methodologies

Have a Great Day!

Warm Regards,

Sania Wadhwa Technical Recruiter Contact Details: 609-755-5388 Email: [email protected] 4365 Route 1 South, Suite 105 Princeton, NJ 08540 www.applabsystems.com