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Physical Design Engineer, Sr Staff

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Onsite

Physical Design Engineer, Sr Staff

Qualcomm

Physical Design Engineer, Sr Staff

Skills

NodePython

1 month ago

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Important information


Contract type:

Permanent

Location:

Bengaluru, Karnataka, India

Work mode:

Onsite

Published on:

23 September 2026

What they need


Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

Job Summary

  • 12+ years of experience in Physical Design, including floorplanning, Place Route (PNR), Clock Tree Synthesis (CTS), and STA signoff checks
  • Hands-on experience owning end-to-end Physical Design from netlist to GDSII, including HM-level PV, LEC, low-power checks, PDN design, and STA closure
  • Experience with voltage islands and low-power design methodologies, flows, and implementation
  • Strong focus on achieving optimal PPA (Power, Performance, Area)
  • Strong familiarity with industry-standard tools such as Fusion Compiler (FC), Genus, Innovus, PrimeTime (PT), Tempus, Voltus, and RedHawk
  • Solid understanding of the full Physical Design flow from floorplanning to post-route optimization and timing signoff, including IR drop analysis and physical verification
  • Experience in implementing complex ECOs for timing convergence across multiple corners using Tweaker, Tempus, and physical ECO flows in PrimeTime
  • Knowledge of power optimization techniques and methods to minimize power consumption
  • Experience in deep submicron technology nodes (preferred)
  • Understanding of high-performance and low-power implementation techniques (preferred)
  • Strong fundamentals in Physical Design and VLSI concepts
  • Proficiency in scripting languages such as Perl, Python and TCL

Roles and Responsibilities

  • Collaborate with cross-functional teams (Design, CAD) to address critical physical design challenges in Camera PNR Implementation.
  • Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets.
  • Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to Camera designs.
  • Partner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs.

Minimum Qualifications

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

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