Physical Design Lead

About Company

Tsavorite Scalable Intelligence is building a new foundation for AI computing. We design silicon, systems, and software that work as one, bringing together general-purpose processing, AI acceleration, and scalable memory in a single architecture. From edge devices to data centers, our goal is to make advanced AI more powerful, efficient, and accessible.

Our founding team has a track record of shipping the highest performance silicon and we have engineering teams in the US and India. We are looking for curious, driven people across disciplines who want to turn ambitious engineering into real products and help shape how the world computes.

Job Summary

We are seeking an experienced Physical Design Lead to drive the implementation and signoff of complex, multimillion-instance, high-speed SoC SubSystems on sub-5nm process nodes. You will own end-to-end convergence across synthesis, place and route (PnR), timing, physical verification, and power delivery network (PDN) implementation.

Technical Skills & Expertise

• Strong hands-on expertise across physical design, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and timing/PPA optimization.
• Hands-on experience with high-performance designs on sub-5nm process nodes.
• Strong experience with advanced-node, high-performance SoC designs.
• Proven ability to push frequency using advanced and custom PnR techniques.
• Expertise in static timing analysis (STA) and ECO generation across PnR stages.
• Ability to independently debug and resolve flow, tool, and design issues.
• Experience with hierarchical SubSystem implementation, including partitioning, budgeting, block abstraction, and top-level physical integration.
• Expertise with industry-standard tools, including Innovus, Tempus, Fusion Compiler, and PrimeTime.
• Proven track record of contributing to physical design flows and methodology development.
• Strong automation skills using TCL, Perl, and Python across implementation stages.
• Experience leading and mentoring engineers and collaborating across design, STA, and signoff teams.

What You'll Drive & Bring to the Role

• Lead RTL-to-GDS implementation for complex SoC, SubSystem, and chiplet-based designs.
• Own execution from floorplanning through placement, CTS, routing, optimization, and signoff, including timing, physical verification, and IR/EM analysis.
• Define implementation strategies and drive frequency, power, area, and complexity trade-offs against product targets and schedules.
• Own PPA convergence against demanding product requirements.
• Drive physical design methodology development for advanced process nodes.
• Partner with RTL architects to identify and resolve timing, congestion, area, and power bottlenecks early in the design cycle.
• Work closely with signoff teams to drive overall design convergence and achieve tapeout targets.
• Demonstrated experience leading physical design execution and driving projects to successful signoff.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related field.
• 10–14 years of work experience.

Why Join Us?

Own. Innovate. Make an Impact.

Join a talented team building next-generation compute solutions and working on cutting-edge technology. Take ownership, collaborate with exceptional engineers, grow your expertise, and make a meaningful impact in a culture that values innovation, technical excellence, and teamwork.

Benefits

• Competitive Compensation aligned with industry benchmarks.
• Comprehensive Health Insurance covering employees and eligible dependents.
• Stock Options & Ownership Opportunities that provide employees with an opportunity to share in the company's growth.