Physical Design Lead

Implementation Lead – Advanced Silicon & AI Hardware

Role Overview

Seeking an experienced Physical Design Lead to drive end-to-end implementation of advanced compute architectures, with a focus on performance, power, area (PPA), and design automation. The role combines hands-on silicon implementation, technical leadership, and AI-driven optimization across complex SoC designs.

Key Responsibilities

• Lead physical implementation of complex ASICs and high-performance compute subsystems from floorplanning through tape-out.
• Own placement, clock tree synthesis, routing, timing closure, and physical sign-off across advanced process nodes.
• Develop and optimize implementation methodologies for large-scale designs, including memory-intensive architectures and high-bandwidth interfaces.
• Integrate machine learning and automated optimization techniques into physical design workflows to improve PPA and execution efficiency.
• Address complex power integrity, thermal, congestion, and timing challenges.
• Develop scalable automation frameworks to accelerate design iterations and improve implementation quality.

Requirements

• 5+ years of hands-on physical design experience, including ownership of complex ASIC or SoC implementations through tape-out.
• Strong expertise in floorplanning, placement, CTS, routing, timing closure, and sign-off.
• Experience with advanced-node implementation and industry-standard EDA tools.
• Exposure to AI/ML-driven EDA optimization, automated design-space exploration, or reinforcement learning techniques.
• Deep understanding of STA, DRC, LVS, EM/IR, and PPA optimization.
• Strong Python and Tcl scripting skills for physical design automation and custom workflows.
• Ability to independently drive technical decisions and lead complex implementation initiatives.