Physical Design Manager

Physical Design Manager

Location: Bangalore

We are a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships.

We are a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services.

We have an urgent open position for " PD Manager " and would appreciate your support in sourcing suitable candidates on priority. Below is the detailed JD for your reference.

• Experience: 12-20 Years
• Work Location: Bangalore
• Work Model: Hybrid (Work from Office)
• Education: B.Tech / M.Tech in Electronics, Electrical Engineering, or related disciplines

Key Responsibilities

• Lead and scale high-performing Physical Design and CAD teams across multiple locations.
• Own end-to-end ASIC/SoC physical implementation including floorplanning, placement, CTS, routing, optimization, and tapeout.
• Drive timing closure, signal integrity, IR drop/EM analysis, DRC/LVS, and low-power verification signoff.
• Collaborate closely with Architecture, RTL, DFT, Analog/Mixed-Signal, Packaging, and Program Management teams.
• Drive methodology improvements, EDA tool optimization, automation, advanced packaging/chiplet flows, and AI-driven design initiatives.

Required Skills

• 12-20 years of experience in ASIC/SoC Physical Design and Timing Signoff.
• Prior People Management Experience is mandatory.
• Minimum 2+ years of experience in a senior management or director-level role.
• Strong hands-on expertise in advanced technology nodes.
• Extensive experience with Synopsys and/or Cadence tool suites.
• Proven experience in full-chip implementation and successful tapeouts.
• Strong understanding of STA, signal integrity, low-power design, UPF/CPF, DRC/LVS, and physical methodologies.
• Deep knowledge of DVFS, power gating, multi-voltage architectures, and high-speed interfaces.

Preferred Skills

• Experience with advanced packaging and chiplet-based architectures.
• Strong leadership, stakeholder management, and team-building capabilities.

Contact: Uday Bhaskar

Mulya Technologies

"Mining the Knowledge Community"

Email id : muday_[email protected]