Platform Signal/Power Integrity Engineer Lead

Job Details Job Description:

Job summary The Platform Signal/Power Integrity (SI/PI) Engineer Lead is responsible for defining, developing, and delivering Signal Integrity and Power Integrity solutions for Intel next-generation validation and product platforms. The role provides technical leadership in platform electrical architecture, high-speed interface implementation, schematic design, PCB layout review, routing guideline development, simulation, validation, and debugging activities. The successful candidate will collaborate closely with silicon, package, platform design, PCB layout, firmware, validation, and manufacturing teams to ensure high-performance, robust, and reliable platform designs that meet electrical, timing, signal quality, and power delivery requirements. Key Responsibilities:

• Lead Signal Integrity and Power Integrity activities for complex platform, board, and package designs.
• Perform pre-layout and post-layout SI/PI simulations and analysis.
• Analyze and optimize: Channel loss Reflection Crosstalk Jitter Timing margin Power delivery network (PDN) performance Power noise and voltage droop
• Develop electrical budgets and design margin requirements for high-speed interfaces.
• Correlate simulation results with laboratory measurements and validation data.
• Drive platform electrical architecture and implementation reviews.
• Perform schematic capture and detailed schematic reviews for complex validation and production platforms.
• Review power architecture, voltage regulator implementation, termination schemes, and interface connectivity.
• Define stack-up, impedance, return path, and power distribution requirements.
• Ensure compliance with platform electrical specifications and design targets.
• Develop and maintain PCB design guidelines and routing constraints.
• Define routing requirements for high-speed interfaces including: DDR4/DDR5 PCIe Gen4/Gen5/Gen6 USB4/Thunderbolt Ethernet CXL High-speed SerDes links
• Conduct PCB layout reviews and provide sign-off recommendations.
• Drive implementation reviews for: Length matching Differential pair routing Reference plane transitions Via optimization Return path continuity Decoupling placement EMI-sensitive routing practices
• Work closely with PCB layout engineers and board vendors to resolve implementation issues.
• Generate and maintain platform SI/PI design guidelines.
• Develop interface-specific routing recommendations and implementation specifications.
• Document design rules, characterization reports, simulation methodologies, and lessons learned.
• Create customer-facing and internal SI/PI collateral supporting platform development and deployment.
• Develop validation methodologies and compliance testing plans.
• Perform electrical characterization and measurements using: Oscilloscopes Vector Network Analyzers (VNA) TDR/TDT equipment Logic analyzers Protocol analyzers
• Debug signal integrity, timing, and power delivery failures.
• Lead root-cause analysis and corrective action activities during board bring-up and validation.
• Lead SI/PI reviews across multiple platform programs.
• Mentor engineers in SI/PI methodology, PCB design practices, and debugging techniques.
• Drive best practices and continuous improvement initiatives.
• Provide technical leadership across platform, silicon, package, and validation organizations.

Qualifications Minimum Qualifications

• Bachelor's, Master's, or PhD degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 9+ years of experience in Signal Integrity, Power Integrity, Platform Hardware Design, or Board Design.
• Strong understanding of high-speed digital design and power delivery architectures.
• Experience with high-speed PCB design and implementation.
• Hands-on experience performing schematic review and board-level electrical analysis.
• Knowledge of transmission line theory, channel modeling, termination techniques, and power distribution network analysis.
• Strong understanding of SI/PI fundamentals, including: Crosstalk Reflection Jitter Eye diagram analysis S-Parameters Power noise Voltage droop
• Proven debugging and root-cause analysis skills.
• Excellent communication and cross-functional collaboration skills. Preferred Qualifications SI/PI Tools
• Experience with: Cadence Sigrity Cadence Allegro Ansys HFSS Ansys SIwave ADS SPICE-based simulation tools Power-aware SI/PI simulation tools Platform Design Experience
• Experience reviewing and signing off: Schematics PCB layouts Routing constraints SI/PI compliance requirements
• Experience defining routing guidelines and electrical design rules for high-speed interfaces.
• Familiarity with package-board co-design methodologies.
• Knowledge of DFM, DFT, and reliability considerations. Interface Expertise Demonstrated experience with one or more of:
• DDR4 / DDR5
• LPDDR4 / LPDDR5
• PCIe Gen4 / Gen5 / Gen6
• USB4 / Thunderbolt
• Ethernet
• SATA
• CXL
• UCIe
• High-speed SerDes technologies

Job Type Experienced Hire

Shift Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.