PMTS - DFT Architect

Job highlights

• Bachelors or Masters degree in computer engineering / Electrical Engineering
• Preferred Experience
• 10+ years of experience in SoC / chiplet and IP design,DFX architecture,or related silicon development disciplines. . Strong understanding of DFX implementation and integration within complex,large-scale SoC / chiplet architectures.

Job Summary

PMTS Silicon Design Engineer

As a member of Circuit Technologies (CT) Team, you will architect, develop, and lead the DFT Design and Integration of cutting edge DFT structures including SCAN, ATPG, MBIST, BSCAN. In this role, you will work with the lead SoC/chiplet and IP architects to define future DFx architectures and contribute to product specifications, micro-architecture specifications, performance, and power trade-offs. The role will work from early concept development through the development phases to final production.

In this role, you will collaborate with a network of expert architects and designers around the world where collaboration and communication skills are critical to the success of this role, and excellent organization skills are essential. You will approach sophisticated problems with a firm methodology and problem-solving technique and conduct experiments and analysis to formulate recommendations and next steps for other colleagues, and SOC/chiplet and IP design teams located in across multiple time zones and geographies. You will formally present your findings to co-workers, teams, and customer engineering teams.

Key Responsibilities

• Develop next-generation SoC/chiplet and IP debug and observability solutions that enable secure, scalable, and robust silicon bring-up, validation, and post-silicon debug.
• Partner with architecture and SoC/chiplet and IP design teams to define and execute a comprehensive Design-for-Excellence (DFX) strategy spanning debug, test, validation, reliability, and manufacturability.
• Collaborate with technology, silicon validation, product engineering, and manufacturing teams to establish DFX architectures that support both functional operating modes and manufacturing test requirements.
• Drive cross-functional alignment on DFX requirements, use cases, and end-to-end implementation flows across AMD engineering organizations.
• Evaluate and deploy AI-driven methodologies to streamline DFX planning, insertion, verification, coverage analysis, and implementation, improving quality, consistency, and scalability while reducing manual effort and time-to-deployment.
• Define metrics, methodologies, and automation frameworks to ensure DFX solutions meet product quality, testability, debug, and production readiness objectives across multiple programs and technology generations.

Preferred Experience

• 10+ years of experience in SoC/chiplet and IP design, DFX architecture, or related silicon development disciplines.
• Strong understanding of DFX implementation and integration within complex, large-scale SoC/chiplet architectures.
• Deep knowledge of DFT methodologies and infrastructure, including scan, ATPG, MBIST, JTAG 1149.x/boundary scan, and advanced debug and test features.
• Solid understanding of SoC clocking, reset, power management, and low-power design architectures.
• Strong analytical, organizational, and communication skills with the ability to collaborate effectively across diverse engineering teams and disciplines.
• Demonstrated ability to decompose complex technical problems, evaluate tradeoffs, and develop solutions from both architectural and implementation perspectives.
• Experience applying AI and data-driven techniques to improve engineering productivity, including DFX requirement analysis, insertion planning, verification, coverage assessment, validation, and design quality optimization.
• Ability to leverage modern AI-assisted engineering workflows and tools to accelerate debug, reduce manual effort, improve consistency, and enable earlier identification of design and DFX risks.

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering

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