Post Silicon Memory Validation Engineer

Post-Silicon Memory Validation Engineer

About the role

We are looking for a motivated and technically strong Post-Silicon Memory Validation Engineer to support the development and validation of memory technologies in next-generation processors. In this role, you will work closely with silicon design teams to develop test and validation features, execute memory validation activities, troubleshoot technical issues, and contribute to the improvement of future processor platforms.​

You will play an important role in ensuring the electrical and functional performance of processor memory subsystems through systematic testing, debugging, and collaboration with cross-functional engineering teams.

Key responsibilities

• Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR5(4)/LPDDR5(4) Memory test experience on electronic components such as uProcessors would be considered a big plus.
• Provides DDR technical leadership in the development of new test & validation features
• Closely interacts with silicon design (DRAM controller and memory PHY) in test execution & debug, as well as in feature definition for future product generation
• Writes comprehensive electrical & functional test plans for the memory validation of processors
• Executes electrical & functional test plans for processors using hardware & software validation tools, oscilloscopes, & logic analyzers
• Debugs electrical & functional issues of the memory sub-system of new processors
• Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors

About you

• Well self-motivated for deliveries and innovation
• Strong technical background on DDR interface
• Good communication skills
• Experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans
• Extensive hands-on experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR
• Familiar with DDR signal measurement, reading schematics and layout documentation
• Good written and oral communication skills
• Familiar with Python, Ruby, Perl language
• Working knowledge of lab equipment such as oscilloscopes, logic analyzers and protocol analyzers