Trilinear Technologies, Inc.
Principal ASIC Design Engineer
2 months ago
Share this opportunity
Share this opportunity to other talents of your network:
✓ Offer them a visibility boost with clients.
✓ Help your contacts find their next job.
Important information
Contract type:
Permanent
Salary:
$150,000 – $200,000 / year
Location:
Tigard, OR, USA
Work mode:
Hybrid
Published on:
17 August 2026
What they need
Principal IC Design Engineer
Who We Are: Trilinear Technologies is a unique organization that offers premium intellectual property and design services from a team of highly experienced video and image processing engineers. Our work can be found in applications ranging from automotive displays to cloud servers to VR head sets. With deep expertise in delivering high quality video systems, Trilinear provides ASIC, FPGA and software solutions to solve complicated customer design challenges.
Who We Want: The ideal candidate will be creative and highly motivated. They will know the difference between getting a job done and getting a job done properly. Knowing the tools and how to code is not enough. The right candidate will understand that quality matters in everything that they produce. The candidate will be a creator and not an integrator. They must understand how to deliver professional quality code on a predictable schedule.
Job Responsibilities:
- Contribute to the design and development of the next generation of semiconductor IP products.
- Develop innovative micro-architectures.
- Deliver high-quality RTL code using SystemVerilog.
- Work with customers to successfully integrate our products into their designs.
Job Requirements:
- 7+ years of industry experience in RTL development.
- Proven experience in complex functional design using Verilog or System-Verilog.
- Block level and system level verification experience using bus functional models and/or verification IP.
- Detailed knowledge of RTL design best practices (test-driven development, high speed design, unit level testing, code reviews, design documentation, continuous integration/continuous delivery, etc.).
- Mentor Questa, Cadence or Synopsys simulation tools.
- Ability to work well with a distributed team.
Preferred Experience:
- Knowledge of complex pipelined architecture designs and/or the DisplayPort interface.
- Successful tape out experience in a 28nm or smaller process.
- Experience with linting tools, CDC and formal verification.
- Familiarity with video and imaging systems.
Job Type: Full-time
Pay: $150,000.00 - $200,000.00 per year
Benefits:
- 401(k)
- 401(k) matching
- Dental insurance
- Flexible schedule
- Health insurance
- Health savings account
- Paid time off
- Vision insurance
Education:
- Bachelor's (Required)
Experience:
- SystemVerilog: 5 years (Preferred)
- IC Design: 4 years (Preferred)
Work Location: Hybrid remote in Tigard, OR 97223
Other offers great for you!
These companies are also looking for great profiles
Espace Freelance
AI Engineer confirmé
Freelance
Paris, France
Hybrid
Skills
1 day ago
Quick apply
Sapiens Group
Consultant·e senior / Lead Design Systems
550€-600€/j
Freelance
Paris, France
Hybrid
Skills
18 hours ago
Quick apply
Soors
Data Engineer H/F
Freelance
Paris, France
Hybrid
Skills
10 hours ago
Quick apply