Principal ASIC Design Verification Engineer

Principal ASIC Design Verification Engineer

Responsibilities

• Architect and develop scalable and reusable test bench environment using the framework of verification methodologies
• Drive test plans for all features for block/core/SOC and write functional coverage for these features
• Build pseudo-random tests to verify and get to full functional coverage and bring the verification to closure
• Debug regression failures, analyze functional coverage gaps, and improve tests to cover the gaps
• Work with other members of the team, guide/mentor junior team members
• Lead the documentation of verification strategy including test plans, verification environment, pseudo-random tests, etc.
• Lead reviews with design/architecture
• Drive verification quality and efficiency improvements

Requires

• BS/MSEE, Electronics or equivalent and at least ten (10+) years of ASIC design verification experience, developing complex verification environments and test plans, analyzing functional coverage, and participating in pseudo-random testing
• Must have gone through at least one full ASIC cycle, from architecture development to tapeout with a full focus on verification leading a core
• Proficiency with SystemVerilog and verification methodologies like UVM/VMM
• Good debug skills in analyzing regression failures and understanding of complex designs
• A good understanding of a complex protocol like PCI-Express or other multi-layered protocol

Preferred

• Experience in PCIe protocol
• Comfort with Makefiles
• Experience verifying other protocols like AXI