Principal ATE Test Engineer

• We are looking for Principal ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions

Benefits

• Flexible time off in the US
• Parental leave
• 401K
• Retirement and pension plans
• Competitive medical, dental and vision plans- The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp
• The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc
• Entrepreneurial, open-mind behavior and can-do attitude
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc
• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred
• ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing
• Strong team player with good communication skills to work alongside a team of high caliber engineers
• Professional attitude with ability to execute on multiple tasks with minimal supervision
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug
• Proficiency in, at least, one modern programming language such as C/C++, Python
• Tester platform selection, design, and development of ATE hardware for wafer sort and final test
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality
• Expertise in production test of high speed SerDes operating at 16Gbps and higher
• Experience with using Teradyne or Advantest 93k ATE platform
• Collaboration with design team to define test strategy, create and own test plan
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests
• Familiar with high-speed load board design techniques
• Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc
• Experience with lab equipment including protocol analyzers and oscilloscopes
• Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms
• Experience in running External loopback at wafer sort
• Fluent in data processing using high level programming languages
• Familiarity with modern databases
• Basic knowledge of RF Testing on ATE Platform