Principal Design Verification Engineer (SerDes/PHY)

• Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems
• This is a high-impact, hands-on role at the heart of Astera Labs’ hyper-growth story. You’ll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world’s most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products
• Verification Architecture & Strategy
• Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers
• Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks
• Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows
• Execution & Coverage Closure
• Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes
• Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios
• Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out
• Physical Layer & Protocol Verification
• Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards
• Model and validate channel behavior, link training state machines, and analog handoff scenarios
• Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks
• Cross-Functional Leadership
• Mentor junior DV engineers and set technical direction across the verification team
• Collaborate with SoC integration, firmware, post-silicon validation, and customer engineering teams
• Contribute to verification IP reuse strategy and tooling improvements across product lines

Benefits

• Flexible time off in the US
• Parental leave
• 401K
• Retirement and pension plans
• Competitive medical, dental and vision plans- Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)
• Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
• Expert-level proficiency in SystemVerilog and UVM
• Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up
• 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP
• MS or PhD in Electrical Engineering or Computer Engineering
• Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP
• Scripting proficiency in Python or Perl for verification automation and regression management
• Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows
• Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results
• Proven ability to lead technically across a multi-disciplinary team in a fast-paced environment