Principal Digital Design Engineer

Responsibilities Lead the definition of system-level requirements and own the digital architecture for

complex digital solutions, including both IP-level and full SoC architectures.

Architect and lead the implementation of complex, reusable RTL modules and top-

level chip integration using Verilog, ensuring adherence to best practices for low-

power and high-performance design.

Own and drive the evolution of the digital design methodology, identifying, evaluating,

and deploying new tools and best practices to enhance efficiency and quality.

Oversee the FPGA validation and pre-silicon emulation strategy, ensuring robust

verification of the entire system and seamless interface between hardware and

software.

Support the overall verification strategy in collaboration with the verification team,

defining success criteria, and ensuring comprehensive functional coverage to deliver

first-pass silicon success.

Collaborate with the physical implementation team to resolve critical timing, power,

and area challenges on advanced technology nodes.

Mentor junior and senior engineers, fostering technical growth and excellence within

the digital design team.

Qualifications Essential: Prospective candidates must have a PhD or Master's degree (or

equivalent) in Electronics or a related field, combined with extensive, proven

experience in a senior or principal digital design role.

Skills, Knowledge, and Aptitudes

Essential

• Expert-level knowledge of digital architectures, ranging from complex

algorithmic IP to full SoC designs including CPU subsystems, interconnect

fabrics (e.g., AMBA/AXI), and system-level protocols.

• Proven track record of leading complex digital architecture and integration (IP

and/or SoC), from specification through to tape-out and silicon validation.

• Mastery of advanced digital design principles, including low-power and high-

speed design techniques.

• Deep understanding and practical application of advanced DFT/DFM

techniques, including scan compression, boundary scan, and memory BIST.

• Expertise in advanced FPGA prototyping and emulation techniques for

complex digital systems.

• Recognized technical leader with the ability to influence and guide cross-

functional teams and make critical technical trade-offs.

• Demonstrated ability to mentor and develop other engineers.
• Exceptional verbal and written communication skills, with the ability to present

complex technical concepts to a wide range of audiences.

Desirable

• Expertise with Cadence or equivalent EDA toolsets for the entire front-end

design and verification flow.

• Experience with functional safety standards such as ISO 26262.