Principal Engineer

About the Role

We are looking for a deeply technical, hands-on senior expert to architect and build our DRAM wafer CP test capability from the ground up. This is not a pure management role — you will roll up your sleeves and personally drive test program development, debugging, and yield optimization while also shaping the overall test strategy and mentoring the team. Split your time between Shanghai and South Korea, working directly with engineering teams and foundry partners on the most challenging technical problems.

What You'll Do

• Personally design, develop, debug, and release production-grade DRAM wafer CP test programs — covering DC/AC characterization, functional patterns, timing validation, and power testing — in full compliance with JEDEC standards and product specifications
• Own end-to-end CP test architecture from 0 to 1: define test methodology, test flow, coverage strategy, and quality criteria; select and deploy ATE platforms, probers, and probe card solutions
• Lead hands-on NPI bring-up — directly engaging in debug/verification, test correlation, failure triage, and smooth transition to high-volume manufacturing
• Drive yield improvement through deep data analysis: dig into yield trends, failure distributions, and parametric shifts to identify root causes and implement test-side fixes
• Perform hands-on electrical failure analysis on failing devices, working closely with teams to resolve the issues and improve test coverage
• Continuously optimize test time, test cost, and throughput by refining test flows, optimizing patterns, and implementing DFT improvements
• Provide technical guidance and mentorship to junior engineers, raising the overall technical bar of the team
• Collaborate cross-functionally and cross-border with design, product engineering, and foundry teams across Shanghai and Korea sites

What We're Looking For

• Bachelor's degree or higher in Microelectronics, Electrical Engineering, Integrated Circuits, or related fields
• 8+ years of hands-on DRAM wafer CP test experience — you still love writing test code and debugging, not just managing teams
• Proven track record of building test capabilities from scratch in a fast-paced environment
• Deep technical expertise in ATE programming (Advantest / Teradyne or equivalent), test pattern development, timing closure, and electrical characterization
• Strong fundamentals in DRAM architecture, memory operation, and JEDEC standards
• Experience with yield analysis, and failure diagnosis at the wafer level
• Ability to thrive in a hands-on, individual contributor (IC) role with strategic scope — you're a technical leader who leads by doing
• Experience working in multi-site / cross-border environments (China / Korea exposure is a strong plus)
• Fluent in English; proficiency in Korean or Mandarin is highly advantageous
• Strong problem-solving skills, attention to detail, and a bias for action