Principal Engineer, DDR & NOC Architecture

We are looking for a Principal-level architect to lead the definition and evolution of next-generation Network-on-Chip (NOC) and DDR memory controller architecture for complex SoCs. This role owns architecture across the on-chip data fabric and external memory subsystem, with responsibility for performance, QoS, scalability, power, reliability, and system-level efficiency.

The ideal candidate brings deep expertise in SoC interconnects, DDR subsystem architecture, performance modeling, and cross-functional technical leadership. They will work closely with system architecture, IP, design, verification, physical design, firmware, and product teams to translate product requirements into robust and production-ready architecture.

• Define end-to-end architecture for NOC and DDR memory controller subsystems in advanced SoCs
• Drive architectural tradeoffs across bandwidth, latency, QoS, coherency, buffering, arbitration, congestion management, power, area, and reliability
• Own memory subsystem strategy, including DDR controller architecture, scheduling policy, traffic shaping, address mapping, refresh impact, and system performance optimization
• Define scalable NOC topology, routing, flow control, bandwidth allocation, and traffic isolation mechanisms for multi-client SoCs
• Develop architecture specifications for interconnect and memory subsystems, including interfaces, performance targets, use models, and corner-case behavior
• Lead performance modeling and analysis to evaluate workload behavior, bottlenecks, utilization, and worst-case traffic scenarios
• Partner with system architects and domain leads to align subsystem architecture with product requirements and software use cases
• Work with RTL, verification, and firmware teams to ensure clean architectural intent, measurable requirements, and efficient implementation
• Review microarchitecture proposals and implementation choices to ensure consistency with system goals
• Drive debug and root-cause analysis for architecture-related issues during pre-silicon and post-silicon phases
• Mentor senior engineers and architects and raise the overall quality of architecture thinking across the organization

Required

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field
• 12+ years of experience in SoC or ASIC architecture with significant ownership of interconnect and memory subsystem design
• Deep expertise in NOC architecture, including topology selection, arbitration, QoS, congestion handling, flow control, and performance optimization
• Deep expertise in DDR memory controller architecture and system behavior under real workload conditions
• Strong understanding of high-performance SoC design tradeoffs across performance, power, area, and scalability
• Experience building architecture models and using data to drive technical decisions
• Strong knowledge of traffic patterns from CPUs, GPUs, AI/ML accelerators, DMA engines, multimedia blocks, and other high-bandwidth clients
• Proven track record of leading cross-functional technical efforts from concept through silicon
• Strong written and verbal communication skills with the ability to influence across architecture, design, and product teams

Preferred qualifications

• Experience with LPDDR and/or DDR architectures used in high-performance and power-constrained systems
• Experience with coherent and non-coherent interconnect fabrics
• Familiarity with cache/memory hierarchy design and system-level performance tuning
• Experience with safety, reliability, ECC, RAS, and functional robustness requirements
• Experience in automotive, AI, edge compute, or other high-compute embedded platforms
• Experience supporting post-silicon tuning and performance characterization

What success looks like

• A clear and scalable NOC and DDR architecture that meets product performance goals without unnecessary implementation risk
• Well-defined architectural specifications that enable efficient execution across design and verification teams
• Early identification of bottlenecks and high-leverage optimizations through modeling and analysis
• Strong alignment across system, hardware, and software stakeholders
• A technically strong team operating with high architectural rigor and clear design intent

Leadership expectations

• Set the technical direction for interconnect and memory subsystem architecture across multiple programs
• Make principled tradeoff decisions grounded in workload behavior and product needs
• Build alignment across diverse engineering teams while maintaining a high bar for technical quality
• Coach and develop senior engineers through reviews, mentoring, and architectural guidance
• Raise organizational capability in performance-driven SoC architecture