Principal Engineer / Senior Engineer / Engineer, PLL Design

Job Responsibilities

• Perform PLL IC design for advanced wireless transceiver and SoC.
• Define CMOS PLL architecture, perform transistor-level design, and conduct chip validation.
• Guide layout and test engineers to achieve excellent jitter, phase noise, and spur performance.
• Participate in system design, application design, testing and evaluation.

Requirements

• Master degree or above in the Electric/Electronic Engineering or related disciplines.
• 5+ years working experience, candidates with more experience will be offered with higher job title according to the HR policy.
• Proficiency in full-custom analog/RF design flow.
• Hands-on experience with RF/mixed-signal lab equipment: high-speed oscilloscopes and spectrum analyzers.
• In-depth understanding of phase noise theory, jitter analysis, VCO pulling/pushing, power supply sensitivity, LO leakage, and spur mechanisms.
• Knowledge on semiconductor devices, device modelling and foundry process.
• Experience on All-digital PLL design or RF transceiver system design is a plus.
• Excellent communication skills in both English and Chinese and strong team spirit.