Principal Engineer - Verification

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

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Job Description

• To play the role of Verification engineer at the Block level verification.
• Develop verification test plans from design specifications.
• Development of test environments using System Verilog and UVM verification methodologies.
• Integration with RTL and basic simulation bring-up for the design.
• Create multiple test cases as per test plan and launch regressions.
• Generate Code/Functional coverage, analyze coverage results and correlate with the test plan.
• Working the design team members to identify and quickly resolve problems with the design.
• Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenge

Requirements/Qualifications

• Bachelor’s/Master’s degree in Electrical / Electronic Engineering or equivalent with atleast 10 year of work experience.
• Domain Expertise : AHB, AXI, PCIe, USB and Ethernet.
• Languages (must): Verilog, system Verilog
• Methodologies (One of them is must): OVM/UVM
• EDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog
• Experience in developing Test Bench components in both block level and SOC level.
• Experience in Creating test plan and Writing test sequence.
• Functional Coverage, Code Coverage & Assertions (OVA, SVA, PSL) (Desirable)
• Good analytical and problem-solving skills
• Excellent written and verbal communication in English.
• Good teamwork and the desire to excel in a competitive environment.
• Bachelor's Level Degree (ECE, EE, CSE, IT / preferred specialization) with more than 10 years of work experience

Travel Time 0% - 25%

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