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PRINCIPAL PHYSICAL VERIFICATION ENGINEER

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Onsite

PRINCIPAL PHYSICAL VERIFICATION ENGINEER

NXP Semiconductors

PRINCIPAL PHYSICAL VERIFICATION ENGINEER

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17 days ago

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Important information


Contract type:

Permanent

Location:

Bengaluru, Karnataka, India

Work mode:

Onsite

Published on:

5 October 2026

What they need


We are seeking a talented Physical Verification Design Engineer to join our VLSI design team. This role involves ownership of full-chip and block-level physical verification (PV) signoff, ensuring designs meet foundry and reliability requirements. The candidate will collaborate closely with physical design, PDK, CAD, and tapeout teams to deliver high-quality silicon.

Key Responsibilities

  • Perform physical verification (PV) for block-level and full-chip designs, including:
    • Design Rule Check (DRC)
    • Layout Versus Schematic (LVS)
    • Electrical Rule Check (ERC)
    • Antenna, density, and reliability checks
  • Drive signoff closure by identifying and resolving PV violations efficiently.
  • Work with physical design and layout teams to debug and fix violations.
  • Develop and maintain runsets, decks, and automation flows using industry-standard tools.
  • Analyze foundry decks and PDK updates, ensuring compliance with process requirements.
  • Lead tapeout readiness reviews and ensure high-quality database delivery.
  • Perform hierarchical verification and regression management.
  • Participate in improving verification methodologies, runtime, and capacity optimization.
  • Interface with foundry and EDA vendors to resolve tool or deck-related issues.
  • Mentor junior engineers and review their work as needed.

Preferred / Added Advantage Skills

  • Exposure to Physical Design (PD) concepts, including:
    • Floorplanning (macro placement, block shaping, congestion awareness)
    • Power Delivery Network (PDN) design (power grid, IR drop considerations)
  • Understanding of:
    • Placement, CTS, routing flows
    • PD-PV interaction and impact of layout decisions on DRC/LVS closure
  • Knowledge of:
    • EM/IR, latch-up, ESD reliability checks
    • Multi-patterning / EUV constraints
  • Experience with full-chip integration and SoC-level challenges
  • Ability to correlate PV issues with PD root causes (e.g., spacing, density, routing hotspots)
  • Exposure to flow automation and methodology development

Soft Skills

  • Strong analytical and problem-solving ability
  • Effective communication across cross-functional teams
  • Ownership mindset with focus on quality and timelines
  • Ability to work independently and guide team members

More information about NXP in India...

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