Printed Circuit Board Designer

About the Role

We are expanding our engineering team in Penang to support high-complexity custom board designs (Reference Validation Platforms / Board of Board form factors, up to 16 layers) featuring next-generation Compute (CPU/SoC), PCD, Graphics (GPU), and Hub components. We have multiple openings for Senior and Mid-Level Engineers specializing in Signal Integrity (SI) , Power Integrity (PI) , or combined SI/PI workflows to drive pre-layout and post-layout simulation, analysis, and tape-out compliance sign-off.

Key Responsibilities

• Signal Integrity (SI) Analysis & Verification:

• Perform pre-layout simulations, topology assessments, and termination studies to guide physical board implementation.

• Execute post-layout simulations including eye diagram analysis, crosstalk evaluation, and skew analysis across multi-layer PCB stackups.

• Validate next-generation high-speed interfaces including DDR5/DDR6, PCIe Gen5/Gen6, USB4, 100GbE+, and emerging technologies against strict compliance specifications.

• Power Integrity (PI) & PDN Optimization:

• Conduct 2D/3D model extraction, Power Delivery Network (PDN) impedance analysis, and noise analysis across die/C4 bumps, silicon, packages, sockets, and boards.

• Perform DC/IR drop simulations across critical power rails to ensure voltage tolerances meet target specs.

• Drive AC decoupling capacitor optimization (delivering updated capacitor BOMs) and power plane resonance analysis with actionable mitigation recommendations.

• Modeling, Correlation & Reporting:

• Set up, maintain, and verify IBIS and SPICE simulation models, perform data correlation, and maintain version control of the simulation model library.

• Deliver comprehensive SI/PI technical reports with clear pass/fail criteria and collaborate in design review meetings to achieve zero critical open issues for board tape-out.

Requirements & Qualifications

• Education: Bachelor's or Master's Degree in Electrical & Electronics Engineering, Computer Engineering, Microelectronics, Physics, or a related discipline.
• Experience Level (Multiple Openings):
• Senior Engineers (5+ years): Deep specialization in either High-Speed SI (with IBIS/SPICE modeling experience) OR PI (with VRM stability and PDN target impedance expertise).
• Mid-Level Engineers (2–4 years): Hands-on experience supporting SI and/or PI pre/post-layout simulations, model setup, data correlation, and technical reporting (candidates who can work with initial guidance and transition into independent execution are encouraged to apply).
• EDA Tool Proficiency: Strong hands-on experience with industry-standard simulation tools such as Ansys SIwave, Cadence Sigrity (PowerDC / OptimizePI), Ansys HFSS, Keysight ADS, or HSpice .
• Work Arrangement: Must be able to work 100% on-site in Penang during standard business hours and meet scheduled project milestone turnaround times. (Part-time / On-demand flex arrangements are also available for experienced mid-level engineers during peak project phases).