Product Application Engineer (PCIe/CXL)

• As an Astera Labs Principal Product Application Engineer, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes
• Regional leads focus on development, debugging, and design-in activities related to customers in a designed geography, and help coordinate with local development teams in Astera Labs Headquarters
• This role will be supporting our China region
• Role is required to work approximately from 12:00 PM to 9:00 PM PST to enable real-time collaboration with stakeholders in the Asia Pacific time zone

Benefits

• Flexible time off in the US

• Parental leave

• 401K

• Retirement and pension plans

• Competitive medical, dental and vision plans

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred

• Silicon/System bring-up and debug experience in customer systems

• Full professional proficiency in Mandarin (written and spoken) required to communicate directly with Asia region customer contacts

• Astera Labs is seeking a Principal Product Applications Asia Region Lead with 8+ years of experience supporting the development and design-in of semiconductor products for PCIe/CXL

• Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 5.0 at a minimum, some experience with 6.0/CXL preferred

• Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs

• Comfort working with software/firmware associated with semiconductor products, such as: Firmware development with C-language, scripting with Python or other equivalent programming languages

• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

• Minimum of 3 years’ experience in designing in complex SoC/silicon products with a high speed (preferably PCIe) interface

• Technical ownership of issue resolution: Driving and directing internal teams toward issue resolution. Driving communication with customers, FAEs, and sales team members

• Development/support for PCIe or Ethernet Switch or Retimer products

• PCIe compliance testing methodology and troubleshooting

• Mandarin language proficiency preferred. Candidate must be able to speak Mandarin to effectively communicate with our China region customers and team members

• Experience with common data center BMC implementation, and BIOS configuration

• Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc

• Triaging complex customer reported issues which require taking into account multiple layers of conditions. For instance, silicon, firmware, hardware board design, and system environment

• Candidate will need to be open work approximately from 12:00 PM to 9:00 PM PST to enable real-time collaboration with stakeholders in the Asia Pacific time zone