R&D Digital Design Engineer

The core switch group (csg) at broadcom focused on developing high-performance ethernet switch silicon and software, primarily targeting hyperscale data centers, cloud providers, and enterprise networks. our group is recognized as an

industry leader in merchant silicon, enabling massive network bandwidth for ai infrastructure and cloud applications.

Our organization works on all levels of ASIC development, spanning high-level architecture to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team as a logic design engineer.as a logic design engineer you will use your knowledge of specifications, mathematics, and computation to write efficient and elegant rtl for implementing components of complex networking asics.

This role requires participation through the full program design lifecycle: developing micro-architecture specifications, RTL implementation, Unit verification, Timing convergence, ECO implementation, debug analysis and reviews.

Qualifications The ideal candidate should exhibit the following behavioral traits:

• Thoughtful and perceptive analytical ability.
• A genuine curiosity for understanding the complete system.
• Dedicated to creative problem solving.
• ability to work independently and at various levels of abstraction.
• Committed to getting things done and executing to plan

Minimum Qualifications:

• B.S. in electrical engineering, computer engineering, computer science, or equivalent.
• B.S. with 8 years of experience, or M.S with 5 years of experience in digital design on multiple networking ASICs.
• 5+ years of experience in verilog based rtl design or verification, in deep submicron technologies.
• Familiarity with Ethernet and other networking protocols.

Preferred Qualifications:

• Extensive experience with Ethernet, TCP/IP, MPLS, tunneling, and other networking protocols.
• Extensive experience with packet processing architectures (packet parsing, acls, metering, policing, etc.)
• Experience achieving timing closure on high performance ASICs in deep submicron technologies.
• Experience with low power design techniques, power estimation methods, clock domain crossing techniques.
• Experience with scripting languages, such as python or perl.

Compensation And Benefits The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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