Research Intern – Adaptive CPU Microarchitecture and Memory Hierarchy

Huawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer-centric innovation and strong partnerships, we have established leading end-to-end capabilities and strengths across the carrier networks, enterprise, consumer, and cloud computing fields. Our products and solutions have been deployed in over 170 countries serving more than one third of the world’s population.

With 20+ sites across Europe and 1500 researchers, Huawei’s European Research Institute (ERI) oversees fundamental and applied technology research, academic research cooperation projects, and strategic technical planning across our network of European R&D facilities. Huawei’s ERI includes the Zurich Research Center (ZRC), located in Zurich, Switzerland. A major element of ZRC is a rapidly growing research laboratory focused on fundamental research in the area of computing systems (new hardware, new software, new algorithms).

The research work of the lab will be carried out not only by Huawei’s internal research staff but also by our academic research partners in universities across Europe. The lab will provide an open research environment where academics will be encouraged to visit and work on fundamental long-term research alongside Huawei staff in an environment that, like the best universities and research institutes, is open and conducive to such world-leading scientific work.

The goal of this project is to improve performance efficiency of next-generation CPUs . The successful candidate will have the unique opportunity to work on groundbreaking ideas related to CPU microarchitecture and affect the future CPU products . Additionally, we offer the opportunity to model and benchmark the performance of the proposed designs by using industry-class simulators and tools.

Responsibilities l Conduct research on next-generation CPU microarchitectures and memory hierarchies.

l Modeling and evaluation of new microarchitectural designs using in-house and/or open-source simulation frameworks.

l Explore intelligent, learning-based components built on AI/ML approaches tailored to microarchitecture, improving the performance efficiency of CPUs.

l Collaborate closely with researchers and product teams to align models with real world constraints.

l Publish and present at top-tier conferences, and share findings with internal experts.

If the areas of CPU microarchitecture and cache/memory hierarchy looks interesting to you, we are looking forward to receiving your application!

Minimum Requirements

• Currently enrolled in a Master’s or PhD program in Computer Science, Computer Engineering, or Electrical Engineering
• Good knowledge of CPU architecture and memory hierarchies
• Experience with architectural simulation platforms

Preferred Requirements

• Currently enrolled in a PhD program in Computer Science, Computer Engineering, or Electrical Engineering
• Hands-on experience with architectural simulation platforms
• Experience with CPU architecture and memory hierarchies
• Knowledge of hardware speculation mechanisms
• Publications in relevant conferences and journals
• Familiarity with ML or reinforcement learning concepts and their application to microarchitectural problems