Research Intern – Hardware Optimization for AI Accelerators

Huawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer-centric innovation and strong partnerships, we have established leading end-to-end capabilities and strengths across the carrier networks, enterprise, consumer, and cloud computing fields. Our products and solutions have been deployed in over 170 countries serving more than one third of the world’s population.

With 20+ sites across Europe and 1500 researchers, Huawei’s European Research Institute (ERI) oversees fundamental and applied technology research, academic research cooperation projects, and strategic technical planning across our network of European R&D facilities. Huawei’s ERI includes the Zurich Research Center (ZRC), located in Zurich, Switzerland. A major element of ZRC is a rapidly growing research laboratory focused on fundamental research in the area of computing systems (new hardware, new software, new algorithms).

The research work of the lab will be carried out not only by Huawei’s internal research staff but also by our academic research partners in universities across Europe. The lab will provide an open research environment where academics will be encouraged to visit and work on fundamental long-term research alongside Huawei staff in an environment that, like the best universities and research institutes, is open and conducive to such world-leading scientific work.

Job Responsibilities:

• Design and optimize arithmetic building blocks for AI accelerators (multipliers, multiply-accumulate and dot-product units) for integer and low-precision floating-point formats, advancing the area/delay/power trade-off.
• Build and apply agentic engineering workflows in which LLM-based agents propose, implement and evaluate RTL and netlist transformations in a closed loop with synthesis, formal verification (equivalence checking) and PPA analysis tools.
• Read and analyze research papers from EDA and computer arithmetic venues (DAC, ICCAD, DATE, ARITH, MLCAD, TCAD, etc.) and reproduce state-of-the-art results as baselines.
• Perform experiments, gather insights, contribute to patents and research papers.

Required Skills:

• Enrolled in a Masters/PhD program or completed Masters in Electrical Engineering, Computer Engineering, Computer Science or a related field.
• Understanding of AI accelerator architectures (e.g., systolic arrays, tensor cores) and the numerical formats used in AI workloads (e.g., INT8, FP8, MX).
• Experience in RTL design (Verilog/SystemVerilog) and Python, and with logic synthesis and digital implementation flows (e.g., Yosys, ABC, OpenROAD or commercial equivalents). Experience with hardware construction languages (e.g., Chisel, Amaranth) is a plus.
• Familiarity with training and inference of ML models (e.g., LLMs, diffusion models, classifiers) and model quantization is a plus.
• Excellent written and verbal communication skills with a proven ability to present complex technical information clearly and concisely to a variety of audiences. Collaborative work style with the ability to work in a multicultural environment.