Rfic Digital Verification Sr Engineer

General Summary

Digital Verification Engineer for IPs, ASICs, and Chipsets used in Qualcomm Snapdragon power solutions.

Job Description

QCT is currently seeking digital verification engineers for the mixed-signal ASICs that support QCTs mobile platforms for next generation 6G RFIC/PMIC/Codec technologies.

Successful candidates will be working on the following:

• Block/Subsystem/SoC level digital verification using constrained-random coverage methodologies at both RTL and Gate Level.
• The skills involved includes SV/UVM/UVM_RAL/Randomization/Coverage/SVA.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience
• OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience
• OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
• Required: Bachelor's, Electronics or EE, 3+ years of work experience
• Preferred: Master's, VLSI, Electronics or EE. 2+ years of experience

Preferred Qualifications

• Experience in writing Test Plans independently
• Experience in writing/updating Verification Testbench
• Experience with debugging RTL Gate level simulations
• Experience with Functional Coverage Code Coverage
• Experience with Scripting in perl, python, tcl
• Experience in planning Verification architecture, review testbench/ testplans with juniors, identify coverage gaps, propose alternate methods for coverage
• Should have been involved in leading a chip DV effort
• Should have been self-driven and quick learner
• Experience with Power aware(UPF) verification and debugs is plus
• Silicon Debug Experience a plus
• Experience with Mixed Signal Designs involving DSP a plus
• Modeling Experience with Matlab, Octave a plus