RISC-V Design Verification Engineer

RVega is hiring on behalf of a semiconductor IP and design services company for experienced verification engineers to work on RISC-V processor cores and subsystems. You will own verification from test planning through coverage closure, working closely with design and architecture teams.

Responsibilities

• Build and maintain SystemVerilog/UVM testbenches for RISC-V cores, subsystems and SoC-level integration.
• Develop test plans from the RISC-V ISA and microarchitecture specifications.
• Run ISA compliance testing and co-simulation against reference models such as Spike or Sail.
• Write constrained-random and directed tests, SVA assertions and functional coverage models.
• Drive regressions, debug failures with designers, and close code and functional coverage.

Requirements

• 4-8 years of hands-on design verification experience.
• Strong SystemVerilog and UVM skills.
• Good working knowledge of the RISC-V ISA: base integer sets, common extensions (M, A, F, C) and the privileged specification.
• Experience verifying processor cores or CPU subsystems.
• Experience with an industry simulator (VCS, Xcelium or Questa).
• Scripting in Python or Perl for regression and automation.

Good to have

• Experience with instruction generators such as riscv-dv or FORCE-RISCV.
• Verification of pipelines, caches, MMU, interrupt controllers (PLIC/CLIC) or the RISC-V debug specification.
• Exposure to formal verification.
• Familiarity with AXI/AHB bus protocols.
• CPU verification on ARM or other architectures, with the ability to ramp up on RISC-V.