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RTL 前端设计工程师

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Onsite

RTL 前端设计工程师

CIP United Co. Ltd.

RTL 前端设计工程师

Skills

Python

1 month ago

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Important information


Contract type:

Permanent

Location:

Shanghai, China

Work mode:

Onsite

Published on:

12 September 2026

What they need


该职位来源于猎聘 岗位职责: 1.负责芯片数字前端设计及soc集成工作,包括数字IP设计实现与仿真,功能模块设计及仿真,系统集成与仿真; 2.完成ASIC到FPGA的设计移植;

  • 配合芯片测试工作及ECO;
  • 编写Sdc时序约束文件; 5.配合后端组完成综合,时序,功耗分析; 任职要求: 1.本科及以上学历,电子类相关专业,五年以上相关工作经验; 2. 熟练掌握verilog/system verilog/vhdl,有较强的脚本(Perl、Python、Shell等)编程能力; 3.最好有以下IP及外设的开发集成经历:Risc-v,PCIE, DDR, Ethernet, MIPI, USB, I2C, UART等等; 4.熟悉计算机体系结构;熟悉常见处理器体系架构,熟悉AXI/AHB/APB总线协议; 5.熟练使用前端相关EDA工具(Lint,CDC,simulation,Synthesis,STA,Power analysis); 6.具备较强的思考问题、分析问题、解决问题的能力和较强的应变能力; 7.具有良好的学习能力、团队精神、责任感、积极主动、沟通能力强;

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