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RTL Des

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Onsite

RTL Des

HCLTech

RTL Des

Skills

GitMachine LearningAI

1 month ago

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Important information


Contract type:

Permanent

Location:

Bengaluru, Karnataka, India

Work mode:

Onsite

Published on:

16 September 2026

What they need


RTL Design Engineer | HCLTech | 7+ Years Experience

Job Description

HCLTech is looking for an experienced and passionate RTL Design Engineer to join our Semiconductor Design team. The ideal candidate will have strong expertise in RTL design, digital logic development, ASIC/SoC design methodologies, and verification. This role offers an exciting opportunity to contribute to the development of next-generation semiconductor products and work alongside industry-leading engineering teams.

Key Responsibilities

  • Design and develop high-quality RTL code using Verilog/SystemVerilog or VHDL.
  • Architect and implement digital logic blocks and complex modules for ASIC/SoC designs.
  • Perform functional verification and collaborate closely with verification teams using methodologies such as UVM.
  • Conduct Static Timing Analysis (STA) and support timing closure activities.
  • Integrate IPs and modules into larger subsystems while ensuring design compatibility and performance.
  • Perform code reviews and ensure adherence to RTL coding guidelines and best practices.
  • Work closely with synthesis, physical design, DFT, and verification teams throughout the design lifecycle.
  • Debug, analyze, and resolve design issues effectively.
  • Stay updated with the latest semiconductor design methodologies, tools, and technologies.

Required Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

  • 7+ years of hands-on experience in RTL Design for ASICs/SoCs.

  • Strong understanding of digital design fundamentals including:

  • Combinational Logic

  • Sequential Logic

  • Finite State Machines (FSM)

  • Clock Domain Crossing (CDC)

  • Reset Architecture

  • Expertise in Verilog, SystemVerilog, or VHDL.

  • Experience with simulation and verification tools such as:

  • Synopsys VCS

  • Cadence Xcelium/Incisive

  • ModelSim/Questa

  • Knowledge of SDC constraints and timing analysis concepts.

  • Excellent debugging, analytical, and problem-solving skills.

  • Strong communication and collaboration abilities.

Preferred Skills

  • Experience with high-performance CPU, GPU, Networking, Storage, or AI/ML semiconductor designs.
  • Exposure to Low Power Design techniques.
  • Familiarity with synthesis flows and ASIC implementation.
  • Experience working with industry-standard EDA tools.

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