RTL Design Engineer 3

Interconnect IP Post Silicon Debug Engineer

The Role:

Are you interested in a role that offers the opportunity to show off your outstanding engineering, creative problem-solving and communication skills?
AMD Infinity Fabric is the scalable coherent interconnect used across all our product segments including EPYC, Ryzen, Radeon, Semi-Custom products, and Deep Learning solutions. This highly visible position will be responsible for Infinity Fabric silicon enablement for one or more products, ensuring performance and power efficiencies, with focus on time-to-market.

The Person:

A successful candidate will:

• Have passion for working on innovative sophisticated computing systems
• Be a self-starter who enjoys finding better and faster ways to solve daring problems
• Be highly organized, able to prioritize, and balance multiple work streams with attention to detail Key

Responsibilities:

• Work closely with Infinity Fabric architects, micro-architects, performance and DV teams to understand new features, arrive at efficient routing configurations, finalize settings, and formulate new silicon test requirements.
• Engage with post-silicon product, platform, validation, and diagnostic development teams to describe and ensure stressing of all new or important design features.
• Engage with firmware/software/modeling teams, deliver initialization/configuration settings, and ensure their correctness.
• Develop debug experiments, tests, and triggers to root-cause functional, performance, and power observations related to the Infinity Fabric IP in post-silicon. Work with HW and SW teams to explore possible alternate solutions or workarounds.
• Collaborate in post silicon power and performance tuning efforts.
• Contribute to the development of scalable debug tools
• Propose and drive Design-For-Debug requirements to the micro-architecture team to aid debug of future designs.
• Participate in discussions on next-generation design ideas, providing feedback based on silicon findings and evolving software usage models.

Preferred Experience:

• Strong background in Computer architecture/microarchitecture, interrupts, memory ordering, MMU, caches and coherency concepts
• Pre-silicon /post-silicon experience on SOC power management debug preferred
• Good understanding of VLSI logic design concepts and power/performance tradeoffs
• Good programming skills in Python, C, Ruby, or Perl
• Familiarity with hardware description languages like Verilog or VHDL
• Comfortable with using lab equipment like oscilloscopes, logic analyzers, etc.
• System debug experience and post-silicon system validation experience a plus Academic

Credentials:

• BS/MS in Electrical or Computer Engineering