RTL DESIGN ENGINEER

RTL Design Engineer

As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence.

The Person

We are seeking an enthusiastic and skilled Design Engineer to join the team within AMD's Adaptive Embedded Computing Group (AECG). In this role, you will be part of a team responsible for architecting, designing, and verifying critical on-chip debug, instrumentation, and testability deployed across AMD's industry-leading FPGA, Adaptive SoC (Versal, Zynq UltraScale+), and custom silicon platforms. You will work across both RTL design and functional verification flows, collaborating closely with software, emulation, and silicon bring-up teams.

Key Responsibilities

• RTL Design Integration:
  • Design, enhance, and integrate digital IP blocks and subsystems using Verilog / SystemVerilog.
  • Work on on-chip debug architectures, JTAG/Boundary-Scan controllers (IEEE 1149.1/1500/1687), data movement datapaths, and packetized debug protocols.
  • Implement and maintain Vivado IP packaging, parameterization, and timing constraints (XDC/SDC).
• Design Verification:
  • Develop and maintain modular, reusable testbenches in SystemVerilog / UVM.
  • Write test plans, functional assertions (SVA), and covergroups based on architectural specifications.
  • Execute constrained-random verification, analyze code/functional coverage, and root-cause RTL bugs.
• Silicon Validation Toolchain Integration:
  • Support pre-silicon emulation (e.g., HAPS/Zebu) and FPGA prototyping environments.
  • Assist in lab bring-up, hardware-software co-verification, and debug tool validation (Vivado Lab Edition, Chipscopy, XSDB).
  • Collaborate with cross-functional teams (Silicon Architecture, Software Tools, Product Applications) to validate IP performance and ease of use.

Preferred Experience

• Experience: 1 - 2 years of relevant industry experience in ASIC/FPGA digital design and verification.
• RTL Architecture:
  • Strong foundation in digital design concepts, synchronous design, clock domain crossing (CDC), and timing closure fundamentals.
  • Proficiency in Verilog / SystemVerilog.
  • Exposure to standard bus protocols (AXI, APB, AHB) and debug interfaces (JTAG, BSCAN, CoreSight).
• Verification:
  • Hands-on experience building testbenches and writing testcases using SystemVerilog / UVM.
  • Experience with standard EDA simulation tools (VCS, Questa/ModelSim, or Xcelium).
  • Understanding of coverage metrics (functional coverage, statement/branch/toggle coverage).
• Scripting Automation:
  • Basic scripting proficiency in Python, Tcl, Bash, or Perl for test automation and flow integration.

Academic Credentials

• Bachelor's or Master's degree in Electronics/Electrical Engineering, VLSI

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