RTL Design Engineer

Job highlights

• Should be capable of defining the Microarchitecture specification from the High Level Architecture spec

• Should have done at least one IP development from the scratch

• Strong experience in RTL coding using Verilog / System Verilog

• Good experience in Synthesis,Lint,CDC,RDC,LEC

• Good communication skills and a team player. .

• Strong experience in RTL coding using Verilog/System Verilog.

• Strong basics of digital design.

• Should be capable of defining the Microarchitecture specification from the High Level Architecture spec.

• Should have done at least one IP development from the scratch.

• Sound knowledge of front end design tools and flows.

• Good experience in Synthesis, Lint, CDC, RDC, LEC.

• Knowledge of niche protocols such as Ethernet, PCIe, DDR, AMBA etc. is a plus.

• Knowledge of Low power RTL design is an advantage.

• Good communication skills and a team player.