RTL Design Engineer

Position: RTL Design Engineer

Location: Penang

• ≥ 3y exp with pre-silicon UVM experience.

• Top tasks focus on CDC/RDC/LINT/Synthesis, upf, timing, integration area.

• RDC (Reset Domain Crossing) Verification of the USB3 Controller with Questa RDC.

• Familiar with synthesis, level type synchronizer, pulse type synchronizer and async fifo.

• Experienced in designs with multiple clock domains/ single bit cross clock domain, sync reset vs async reset, CDC checks, RDC checks.

• Experience in analog mixed signal design.