RTL Design Engineer - Low Power and Front-End Quality

Job highlights

• Experience: 5+ Years . : We are seeking an experienced RTL Design Engineer with a strong background in multi-clock and multi-voltage domain design,front-end quality checks,and low power methodologies
• The ideal candidate should have hands-on experience in front-end flows such as Lint,CDC,Synthesis,and LEC,along with a good understanding of memory or cache controller subsystems

Location : Bangalore

Experience: 5+ Years

Job Description:
We are seeking an experienced RTL Design Engineer with a strong background in multi-clock and multi-voltage domain design, front-end quality checks, and low power methodologies. The ideal candidate should have hands-on experience in front-end flows such as Lint, CDC, Synthesis, and LEC, along with a good understanding of memory or cache controller subsystems.

Key Responsibilities:
Design and verify multi-clock and multi-voltage domain systems.
Perform RTL front-end quality checks, including Lint, CDC, Synthesis, LEC, and Low Power checks.
Ensure RTL quality and adherence to design standards across the front-end flow.
Work closely with Subsystem and/or SoC Integration teams for design integration, debug, and signoff.
Apply UPF-based low power design techniques and perform related verification checks.
Collaborate with architecture and verification teams to meet performance, power, and functionality targets.
Contribute to automation and process improvement initiatives within the design flow.

Required Skills and Experience:
Experience in multiple clock and voltage domain design.
Working knowledge of front-end flows: Lint, CDC, Synthesis, and related quality checks.
Understanding of UPF and Low Power design/verification.
Familiarity with memory subsystems, such as Memory Controller or Cache Controller.
Experience in RTL integration and debugging at subsystem or SoC level.
Strong analytical, problem-solving, and debugging skills.