RTL Design Engineer (Spyglass / CDC / Low Power / Wireless Modem IPs)

Job highlights

• Experience: 5+ Years .
• Experience with wireless modem IPs or similar high-performance digital blocks is a plus
• Hands-on experience with tools like Spyglass,0-in,Design Compiler,PrimeTime,and simulation environments

Location : Bangalore

Experience: 5+ Years

Mandatory Skills :

Spyglass, RDC, CLP, PLDRC, CDC, DC-Compiler,
.Strong expertise in Verilog/System Verilog RTL coding and micro-architecture development.

Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable.
.Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic.

Experience with wireless modem IPs or similar high-performance digital blocks is a plus.

Familiarity with low-power design methodologies and CDC handling.

Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments.

Exposure to post-silicon debug and SoC integration challenges.

Knowledge of Design Tool Flows including Spyglass, RDC, CLP, PLDRC, CDC, DC-Compiler, Prime time, synthesis, simulation etc
.