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RTL Design Professional

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Onsite

RTL Design Professional

Proxelera

RTL Design Professional

Skills

Python

2 months ago

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Important information


Contract type:

Permanent

Location:

Bengaluru, Karnataka, India

Work mode:

Onsite

Published on:

14 October 2026

What they need


Job highlights

  • Experience: 3-8 Years (Minimum 3yrs of experience in RTL Coding)
  • Of Position: 10 . Work Location: Bangalore . We are seeking an RTL Design Engineer with strong hands-on coding experience in Verilog / SystemVerilog
  • . 3-6 years of experience in RTL design and development . Strong expertise in Verilog / SystemVerilog coding . .

Job Title: RTL Design Engineer - 3-8Yrs
Experience: 3-8 Years (Minimum 3yrs of experience in RTL Coding)

No. Of Position: 10

Work Location: Bangalore

We are seeking an RTL Design Engineer with strong hands-on coding experience in Verilog/SystemVerilog. The role involves developing high-quality, synthesis-ready RTL for complex SoC/IP designs, with a focus on clean, efficient, and scalable design implementation.

Key Responsibilities:

  • Develop high-quality RTL code (Verilog/SystemVerilog) for digital IPs and SoC components

  • Translate architecture and specifications into efficient, synthesizable RTL

  • Design modules with focus on performance, power, and area (PPA) optimization

  • Perform RTL simulation and unit-level validation

  • Ensure RTL quality through lint, CDC, and synthesis checks

  • Debug and fix functional, logical, and integration issues

  • Collaborate with verification, architecture, and physical design teams

  • Participate in design and code reviews to ensure best coding practices

    Required Skills:

  • 3-6 years of experience in RTL design and development

  • Strong expertise in Verilog/SystemVerilog coding

  • Solid understanding of digital design concepts (FSMs, pipelining, arbitration, datapath/control design)

  • Experience writing clean, modular, and reusable RTL

  • Familiarity with synthesis tools (e.g., Design Compiler or equivalent)

  • Knowledge of timing concepts, CDC, and basic low-power techniques

  • Strong debugging and problem-solving skills

    Preferred Qualifications:

  • Experience with SoC/IP design (e.g., AXI/AHB/APB, memory controllers, or custom IPs)

  • Exposure to low-power design (UPF)

  • Familiarity with DFT considerations in RTL design

  • Scripting skills (Python/Perl/Shell)

  • Understanding of backend/physical design flow

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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