RTL Design (UCIe/PCIe) Architect

Job highlights

• 12-20+ years in protocol/IP development with deep PCIe Gen4/5/6 and UCIe architecture expertise
• Lead architecture, integration, and verification strategy for high-speed connectivity IPs and chiplet interconnects, define subsystem architecture, drive protocol compliance, and guide verification teams

Your Role

Lead architecture, integration, and verification strategy for high-speed connectivity IPs and chiplet interconnect solutions.

• Define PCIe/CXL/ UCIe subsystem architecture.
• Drive protocol compliance strategy.
• Review integration architecture and performance requirements.
• Lead interoperability and compliance planning.
• Guide verification and validation teams.
• Interface directly with customer architects.
• Support roadmap and future standard adoption.

Your Profile

• 12-20+ years in protocol/IP development.
• Deep expertise in PCIe Gen4/5/6.
• UCIe architecture expertise.
• Chiplet ecosystem experience.
• Strong knowledge of protocol stack and LTSSM.
• Experience with root complex, endpoint, switch architectures.
• Experience integrating PCIe into large SoCs.
• Strong architecture and verification background.
• Knowledge of SerDes architecture.

Good to Have

• CXL protocol knowledge.
• HBM integration.
• Protocol compliance testing.
• System-level performance modeling.

What Youll Love About Working Here

• Opportunity to work on high-speed connectivity IPs.
• Collaborative work environment with focus on innovation and professional growth.
• Continuous learning opportunities to enhance technical and domain expertise.