RTL Design Verification Engineer

Design Verification Engineer

PQAngels Technologies Pvt Ltd
Experience: 4-11 Years | Location: Bengaluru, Hyderabad, Chennai | Employment Type: Full-Time

About Company
PQAngels is a product engineering company built for the silicon-to-software stack. Founded by engineers, we help
customers accelerate innovation through Semiconductor, ASIC, VLSI, Embedded and Product Engineering services.

Role Summary
We are seeking experienced Design Verification Engineers with strong UVM expertise for SoC/IP verification.

Key Responsibilities
Develop verification plans.
Build reusable UVM environments.
Functional coverage closure.
Assertions and debugging.
Regression execution.
Testbench development.
Root cause analysis.
Protocol verification.
Customer interactions.
Documentation.
Verification signoff activities.
Collaborate with RTL and PD teams.

Mandatory Technical Skills
SystemVerilog
UVM
SVA
Functional Coverage
Protocol Verification (AMBA , AXI, APB, AHP, PCIe, DDR, USB, Ethernet)
Python/TCL

EDA Tools
VCS
Xcelium
QuestaSim
Verdi

Qualifications
Bachelor's or Master's degree in Electronics, Electrical, ECE, VLSI, Microelectronics or related field.
Soft Skills
Strong communication, analytical thinking, stakeholder management, problem solving and ability to work in global
teams.

Pay: ₹100,000.00 - ₹200,000.00 per year

Benefits:

• Flexible schedule
• Leave encashment
• Paid sick time
• Provident Fund

Work Location: In person