RTL Engineer

Job Description: Simulation Migration Engineer(SV/UVM)

Experience: 5 Years

Location: Hyderabad

Key Requirements:

• Strong hands-on experience in SystemVerilog (SV) and UVM methodology
• Experience in simulation migration activities, specifically from VCS to Xcelium (Exilium)
• Good understanding of low power verification concepts
• Expertise in functional verification, including testbench development and execution
• Strong skills in coverage analysis (functional & code coverage)
• Proficient in debugging simulation issues and regression failures
• Experience in verification environment bring-up and migration support

Roles and Responsibilities
Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.