RTL Integration (Frontend) Engineer

Job highlights

• Preferred Qualification: . Cadence tool chain experience .

• Experience with RTL rule checkers (Lint),CDC,RDC,LEC .

• Experience in RTL design,Synthesis,Static Timing Analysis,RTL and Netlist Power Analysis . Good understanding of Gate level netlists and Physical design flows .

• Experience with scripting languages such as perl / python

• Own the IP integration into ASSP/SOC

• Integrated EdgeCortix DNA IP and other third-party IP integration

• Experience with RTL rule checkers (Lint), CDC, RDC, LEC

• Solid proficiency with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile)

• Experience in RTL design, Synthesis, Static Timing Analysis, RTL and Netlist Power Analysis

• Good understanding of Gate level netlists and Physical design flows

• Playing a key role in development of verification infrastructure, which would involve VIPs, different memory models, monitors, etc.

• ECO Flows, Elab checks, Physical Synthesis

• Integration flow automation and improvements

• Generating Design Constraints and Constraints Analysis

Desired Qualifications:

• 4-7 years of relevant experience covering RTL integration and front end design checks, STA, PPA
• Knowledge of Chisel based environments
• IP knowledge of PCIe/UCIe, AXI, DDR, NIC
• RISC V integration experience is a plus
• FPGA integration experience
• Formal equivalence

Preferred Qualification:

• Cadence tool chain experience
• Prior CPU/Memory/Bus Integration at subsystem level.
• Good understanding of Physical design flows
• Strong Synthesis , Timing Analysis and Power Analysis experience
• Experience with scripting languages such as perl/python