RTL / IP Design

Job highlights

• You have 5+ years of experience of digital ASIC front-end design . Have a good understanding of the design flow like RTL (VHDL,Verilog and / or SystemVerilog) . Have experience of simulation tools like Questa or Xcelium and logic synthesis (e.g

• You have 5+ years of experience of digital ASIC front-end design

• Have a good understanding of the design flow like RTL (VHDL, Verilog and/or SystemVerilog)

• Have experience of simulation tools like Questa or Xcelium and logic synthesis (e.g. Synopsys DC).

• You have experience of embedded microcontrollers and AMBA bus systems.

• You have a science/engineering Bachelors degree and you speak English fluently.