RTL Verification Engineer

What You ll Do

• Plan and execute RTL verification of SoCs and IPs from scratch to closure.
• Develop and maintain UVM-based testbenches with functional coverage and assertions.
• Debug gate-level simulations and analyze waveforms using industry-standard tools.
• Write and manage verification environments using SystemVerilog, UVM, and scripting languages.
• Collaborate with design, architecture, and system teams to deliver high-quality silicon.
• Contribute to power-aware verification and verification methodology improvements.

What Were Looking For

Required:

• 5-6 years of verification experience or 4+ years with exceptional background/Masters/PhD .
• Bachelors in Engineering/Science with a GPA of 9+ from IITs, NITs, or Jadavpur University.
• Strong expertise in SystemVerilog, UVM, assertions, coverage, and waveform debugging.
• Proven ownership of end-to-end RTL verification for SoCs or multiple IPs.
• Experience with gate-level simulation and power extraction tools.
• Scripting skills Python/Perl/Tcl for automation.
• Excellent communication and documentation ability.

Preferred:

• Experience with DSP, processor design/verification, and AXI, MIPI, PCIe protocols.
• Knowledge of wireless communication blocks and circuits.

Compensation Benefits

• Base salary: Competitive and based on experience
• Cash bonus + meaningful early-stage equity
• Relocation bonus, partner job-search help
• Health insurance, paid leave, performance incentives, and employee rewards

Why Join Us

• Work on deep tech that matters
• Collaborate with world-class experts and industry leaders
• .Own your work end-to-end and see real impact
• Enjoy a culture of speed, rigor, and respect
• Competitive salary, equity, and global exposure

Keywords: RTL Verification, SystemVerilog, UVM, SoC, Wireless Circuits, AXI, MIPI, Gate-Level Simulation, Startup, Digital Design, Coverage

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