RTL Verification Lead

Job Title: RTL Design Lead - 10-12 Yrs

Experience required: 10-12 years

Location: Bangalore

No. Of positions: 1

Work Mode: Onsite(all 5 days)

Education: Bachelors and/or Masters in Electronic engineering

Round of interviews: 2
R1: F2F
R2: F2F(Both interviews will happen on the same day)

Top 3 mandatory (primary) skills:

• Verilog, system verilog, UVM
• IP level TB component development
• Mastery in EDA tools (Verdi,vcs) etc

Good to have (secondary) skills:

• Comfortable in scripting for automation
• AI tools usage
• Experience in digital+analog verification

Soft Skills: Converse with teams across various geographies

Job Description

• Scope: Owns IP and top-level ASIC verification for complex SerDes subsystems.
• Domain: Verifies digital RTL integrated with analog behavioral models using SystemVerilog/UVM.
• Alignment: Ensures seamless functionality across digital, analog, and firmware boundaries.
• Metrics: Drives testbench architecture and test planning to achieve coverage closure.

Job Responsibilities / Day-to-Day Activities

• Spec Review: Analyze design specs and collaborate with designers to align test plans.
• Testbench Development: Build or upgrade UVM testbenches, write tests, and close coverage.
• Cross-Team Integration: Work with RTL, analog, and firmware teams to bridge design gaps and verify system-level interfaces.
• Behavioral Model Verification: Validate subsystem functionality including analog model and firmware interactions in the digital testbench.
• Productivity: Leverage approved automation and AI tools to accelerate debugging and triage.

Strong requirement for IP-level verification skills, exposure to AI tools and system-level exposure ( VnC, SoC bringup, GLS, firmware etc).

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.