Senior Analog Layout Engineer

Role and Responsibilities

• Implement the design and physical implementation of analog, mixedsignal, custom digital blocks and support fullchip integration, using a combination of traditional layout expertise.

• Own blocklevel layout execution with strong focus on quality, turnaround time and design intent.

• Perform layout verification activities, including DRC, LVS, Antenna checks, Yield and quality checks.

• Deliver ontime, highquality blocklevel layouts under the guidance from senior engineers.

• Use promptbased AI tools to Generate or refine SKILL/Python/TCL scripts, automate repetitive layout and verification tasks to reduce manual effort and improve layout consistency.

• Support custom and digital layout integration, using semicustom tools to accelerate ECOs, alignment, and integrationlevel updates.

• Collaborate closely with Design, Verification, CAD, and senior layout engineers, clearly communicating layout status and risks.

• Assist in reviewing subblock layouts from engineers developing their skills and share helpful techniques within the team.

Job Requirements

• 3+ year experience in analog/custom layout design in advanced CMOS process.

• Handson experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, including ownership of verification and closure for assigned blocks.

• Experience in layout of critical analog and mixedsignal blocks like Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps

• Exposure to memory layout environments, including DRAM, SRAM, CAM or OTP is desirable.

• Solid understanding of analog layout fundamentals, including Matching and symmetry techniques electromigration, latchup, IRdrop, Coupling, crosstalk and parasitic effects.

• Understanding of layout impact on circuit performance, including speed, capacitance, power, and area.

• Ability to interpret design constraints and translate them into robust, manufacturable layouts.

• Handson experience in developing or applying AIdriven automation and AIassisted methodologies to improve efficiency and quality of physical layout tasks.

• Strong problemsolving skills in physical layout verification and debug.