Senior Analog Layout Engineer_2026

Responsibilities:

• Development of innovative analog layout ( floor planning, device placement, matching and routing, LVS, DRC, DFM check and reliability verification ) and solving technical issues in different process technologies.
• Responsible for layout optimization, post layout extraction and parasitic analysis.
• Collaborate with Design Lead, Circuit designers, and Layout engineers to implement custom IPs and archive full chip integration, place and route, top level verification and tape out.
• Deliver quality engineering work that meets and exceeds customer expectations all the time
• Guide and coach juniors by ensuring their works meets the desired area, performance and power consumption.

Job Requirements:

• Minimum 3 years of experience in analog IC layout
• Experience in Cadence Virtuoso, Calibre Verification (DRC, LVS) is preferred.
• Familiar with Analog Custom Layout : PLL, Amplifier, DLL
• Hand on experience in memory compilers / SRAM / RAM / ROM is a plus

For interested applicants, kindly send your resume in Word/PDF format to include the following in your resume including:

1. Current Salary

2. Expected Salary

3. Availability

4. Reason for leaving

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