Senior ASIC Design Engineer

We are looking for a Senior ASIC Design Engineer to join our growing team in Singapore.

Key Responsibilities:

• Micro-architecture & RTL development for AI compute subsystems.
• Analyze performance, power, and area (PPA) to deliver high-performance compute within strict cost and energy budgets.
• Contribute to RTL design of SoC modules and assist in IP core integration.
• Support chip-level system design tasks, including clock/reset architecture, low-power design techniques, and bus architecture.
• Collaborate with verification and testing teams to perform module-level and system-level validation.
• Assist front-end engineers in netlist delivery and help resolve timing issues.
• Provide support for driver development, debugging, and technical documentation.

Requirements:

• Bachelor’s degree or higher in Electrical Engineering (or equivalent).
• 3 years or above of relevant experience in digital IC/ASIC design.
• Strong understanding of digital circuit fundamentals and proficiency in Verilog HDL.
• Familiarity with ASIC design flow and EDA tools (e.g., Synopsys, Cadence).
• Good understanding of CPU and Cache architectures, instruction set architectures (ISA), and compiler principles.
• Knowledge of bus systems, DMA, and peripheral interface design.
• Awareness of low-power design methodologies.

Preferred Qualifications:

• Familiarity with standard bus protocols (e.g., AMBA, AXI, AHB, APB).
• Exposure to synthesis, timing analysis, or DFT concepts.
• Good problem-solving skills and eagerness to learn in a collaborative environment.
• Strong communication skills and ability to document technical work clearly.