Senior ASIC Implementation Engineer

Job highlights

• Bachelors degree in Science,Engineering,or related field . 4+ years of ASIC design,verification,validation,integration,or related work experience
• Minimum Qualifications
• Preferred Qualifications
• Professional ASIC hardware design and / or implementation experience
• Strong experience with industry standard synthesis tools .

Senior ASIC Implementation Engineer

We are seeking a highly skilled Senior ASIC Implementation Engineer to join our team.

The successful candidate will be responsible for a range of key ASIC implementation tasks, including but not limited to synthesis, timing constraints, implementing ECOs, STA, Power intent implementation & validation, lint, power analysis, CDC RDC Analysis & Validation. You will also model and analyze performance, area, power, and system cost tradeoffs for different micro-architectures and contribute to implementation methodologies and flows.

Specific responsibilities will be a function of project and team needs and may vary over time. In addition to implementation tasks the successful candidate may also be asked to perform ASIC design tasks including some RTL development, or physical design activities from floor plan definition to P&R and participate in creative problem solving as part of a crossdisciplinary design team.

Responsibilities

• Professional ASIC hardware design and/or implementation experience.
• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
• Debug the timing/area/congestion issues in physical implementation and work with RTL & Physical desig teams to resolve them
• Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities
• Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures
• Perform RTL Lint and work with the Design team to create waivers
• Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC
• Develop Power Intent Specification in UPF for the multi-Vdd designs.
• Use Conformal ECO flow, and able to implement complex large ECOs
• Take a part in PD activities from floor planning to P&R

Minimum Qualifications

• Bachelors degree in Science, Engineering, or related field
• 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Strong experience with industry standard synthesis tools
• Hands on experience with checking tools for Lint, CDC, RDC, CLP
• Solid understanding of STA fundamentals and SDC writing experience
• Scripting skills (Python , PERL, TCL)

Preferred Qualifications

• 8 + years of ASIC design-related experience with successful tape-outs in advanced process nodes
• Working knowledge of UPF specification and in depth understanding of power planning implications and physical implementation challenges
• Experience with High-speed/Low power ASIC design within a Unix environment
• Experience with clock domain crossing techniques and tools
• Hands-on experience in multiple Physical Design areas such as Floorplanning, Place and Route, Macro and Pin placement, Power Planning and resolving typical issues.
• Strong communication (written and verbal) and interpersonal skills as a member of cross disciplinary team
• Detail oriented with strong analytical and debugging skills