Senior ASIC Physical Design Engineer

📍 Zürich, Switzerland | Hybrid | Permanent

Experienced in ASIC Physical Design, Static Timing Analysis (STA) and Timing Closure?

We are supporting an innovative semiconductor technology company in Zürich looking for a Senior ASIC Physical Design Engineer to join its growing engineering team.

This is an opportunity to work on advanced ASIC and SoC designs, tackle challenging timing and implementation problems, and take real ownership of physical design and sign-off activities.

🚀 What you will be working on

• ⏱️ Driving STA, timing closure and sign-off across complex ASIC/SoC designs
• ⚙️ Working with synthesis, place & route (P&R) and clock-tree synthesis (CTS) teams
• 🔍 Developing timing constraints and resolving setup/hold violations
• 🛠️ Supporting timing optimisation and ECO implementation
• 🧩 Collaborating with digital and custom IC teams to integrate complex IP blocks
• 💻 Improving design flows and automating analysis using Python or Tcl

🎯 What we are looking for

• 5+ years of professional ASIC Physical Design / Backend experience
• Strong hands-on experience with STA, timing closure and sign-off
• Good understanding of synthesis, P&R, CTS and timing constraints
• Experience resolving timing issues across different operating corners and modes
• Scripting skills and familiarity with industry-standard EDA tools
• A collaborative, problem-solving approach

✨ Bonus points for experience with advanced semiconductor nodes, low-power designs, memory-related IP, AI accelerators or complex SoC integration.

🌟 Why consider this opportunity?

• 🧠 Work on innovative semiconductor and computing technology
• 🔬 Solve complex technical challenges with real ownership and influence
• 🚀 Contribute to the development of advanced ASIC/SoC products
• 🤝 Collaborate with experienced engineers across different design disciplines
• 🏠 Flexible hybrid working arrangements in Zürich