Senior Chip Design Dynamic Verification Engineer

We are now looking for a Senior Chip Design Dynamic Verification Engineer to join our Switch Silicon team. As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What You'll Be Doing:

• Work in a design/verification team which develops core units within the Switch silicon as a dynamic verification or RTL design engineer.
• Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.
• Design RTL of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
• RTL synthesis, timing, supporting verification, and silicon post TO activities.
• Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

What We Need To See:

• Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
• 5+ years of experience in chip design.
• Knowledge in network protocols and/or HPC and distributed calculations - advantage.
• A team player with good communication and interpersonal skills.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field.