Senior Circuit Design Engineer

Responsibilities

• Work on the following IPs but not limit to: Non-volatile memory IPs, SRAM，ADC/DAC, LDO/DCDC, POR, BOR, Band-gap, various amplifiers, PLL/DLL and high speed interface design
• Guide layout engineers in completing the physical design of NVM memory arrays and peripheral analog modules
• Support the generation of NVM IP DK (Design Kit), including Verilog, Liberty, datasheet, bitmap, etc.
• Support the design and testing of related NVM testchips
• Follow company’s quality standards during any project execution

Requirements

• Bachelor's or Master's degree in Microelectronics or related field. At least 3 years of direct experience in analog and mixed-signal transistor-level circuit design
• Proficient in using mainstream analog design EDA tools, including Cadence Virtuoso, Spectre, HSPICE, XA, FINESIM, etc., for full-custom circuit design and simulation
• Experience on design with advanced process nodes such as CMOS, Fin-FET, and FD-SOI
• Experience with memory design is highly desirable
• Knowledge with process and physical layout is a plus
• Excellent technical document read and writing skills in both Chinese and English, as well as strong communication and coordination skills, able to collaborate effectively with layout, test, and system teams