Senior CPU Design Verification Engineer – CPU / SoC / SystemVerilog / UVM

Senior CPU Design Verification Engineer – CPU / SoC / SystemVerilog / UVM

We are currently partnered with a semiconductor technology organisation developing CPU and SoC architectures. They are looking to hire a Senior CPU Design Verification Engineer to work closely with CPU and SoC architects, validating microarchitectural concepts and ensuring selected areas of CPU design are thoroughly verified and ready for product launch.

The role covers verification planning, methodology development, testbench and verification environment development, regression execution, debug, and coverage tracking across a defined functional domain.

Key responsibilities

• Work closely with CPU and SoC architects to understand architectural concepts and high-level system requirements
• Develop detailed test and coverage plans based on CPU architecture and microarchitecture
• Develop scalable and portable verification methodologies across different environments
• Develop verification environments and their associated components
• Develop stimulus, checkers, assertions, trackers, and coverage mechanisms
• Develop verification plans and testbenches for the assigned functional domain
• Execute verification plans throughout the design verification lifecycle
• Perform design bring-up and verification environment bring-up
• Enable regressions covering features within the assigned area
• Debug test failures and support resolution of verification issues
• Track and report design verification progress using metrics including bugs and coverage
• Support validation of CPU and SoC microarchitectural concepts through to launch readiness

Key requirements

• Experience in CPU design verification
• Experience working with CPU and SoC architectures and microarchitectures
• Experience developing detailed verification and coverage plans
• Experience developing verification methodologies
• Experience developing scalable and portable verification environments
• Experience developing verification environments and testbenches
• Experience with stimulus generation, checkers, assertions, trackers, and coverage
• Experience executing verification plans and regressions
• Experience with design and verification environment bring-up
• Experience debugging verification test failures
• Experience tracking verification progress using bugs, coverage, and related metrics
• Ability to work closely with CPU and SoC architecture teams

Keywords

Senior CPU Design Verification Engineer / CPU Verification Engineer / CPU DV Engineer / Design Verification Engineer / CPU Verification / Processor Verification / CPU Design Verification / SoC Verification / SoC Design Verification / CPU Architecture / SoC Architecture / CPU Microarchitecture / Microarchitecture Verification / Verification Methodology / Verification Planning / Test Planning / Coverage Planning / Functional Coverage / Verification Environment / Verification Infrastructure / Testbench Development / Testbench / Stimulus / Checkers / Assertions / Trackers / Regression Testing / Regression / Design Bring-Up / DV Environment Bring-Up / Verification Debug / Test Failure Debug / Bug Tracking / Coverage Analysis / Verification Metrics / Functional Verification / Hardware Verification / Semiconductor Verification / ASIC Verification

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