Senior Design Engineer

🚀 Now Hiring: Sr. Design Engineer (ASIC/FPGA)

📍 Location: Remote (Must be willing to relocate for onsite work if converted to a full-time employee)

🕒 Schedule: Monday-Friday | Standard Business Hours

📄 Job Type: 6+ Month Contract (Potential Extension and/or Direct Hire Based on Performance)

We are seeking an experienced Sr. Design Engineer with a strong background in ASIC and FPGA design, verification, and implementation . This role offers the opportunity to work on cutting-edge digital and mixed-signal designs while collaborating with multidisciplinary engineering teams.

Key Responsibilities

• Design and develop digital ASICs, FPGAs, and mixed-signal ASIC solutions.
• Develop and implement RTL using VHDL, Verilog, and/or SystemVerilog .
• Create verification methodologies, test benches, coverage models, and test plans.
• Perform timing analysis, noise analysis, and other signoff activities.
• Collaborate closely with systems, firmware, architecture, and product engineering teams.
• Support lab integration, debug, validation, and troubleshooting efforts.
• Resolve implementation challenges related to timing closure, congestion, and design optimization.

Required Qualifications

• 7+ years of ASIC and FPGA design experience.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Strong proficiency in VHDL, Verilog, and/or SystemVerilog .
• Experience with design verification and test bench development.
• Familiarity with Linux development environments.
• Experience across ASIC/FPGA design and implementation workflows.

Preferred Qualifications

• Master's or PhD in Electrical Engineering, Computer Engineering, or related field.
• Experience with the complete ASIC/FPGA lifecycle including architecture, design, simulation, verification, validation, integration, and testing.
• Knowledge of Software-Defined Radio (SDR), ADC/DAC, and DSP architectures .
• Understanding of communication systems, modulation techniques (QPSK, QAM, PCM/FM, PAM), spread spectrum, and forward error correction.
• Programming and scripting skills in Python, TCL, and Perl .
• Experience with industry-standard EDA tools, physical design flows, and RTL-to-GDSII implementation.
• Knowledge of FinFET and CMOS technologies.
• Experience with DFT methodologies including Scan, MBIST, and LBIST.
• Prior experience mentoring junior engineers is highly preferred.

Desired Skills

ASIC Design | FPGA Design | RTL Design | SystemVerilog | Verilog | VHDL | Design Verification | UVM | Linux | Timing Analysis | Signal Integrity | EDA Tools | Physical Design | RTL-to-GDSII | SDR | DSP | ADC/DAC | Python | TCL | Perl | DFT | MBIST | LBIST | FinFET | CMOS

📩 If you're interested in exploring this opportunity, apply today or reach out directly for additional details.

#ASIC #FPGA #RTLDesign #SystemVerilog #Verilog #VHDL #DigitalDesign #ElectricalEngineering #HardwareEngineering #Semiconductor #EngineeringJobs #RemoteJobs #HiringNow #DesignEngineer #ASICEngineer #FPGAEngineer